1. Field of the Invention
The present invention is directed to a bipolar mode field effect transistor (BMFET) technique, and more particularly to a lateral BMEFT formed on a silicon-on-insulator (SOI) substrate and a method for manufacturing the same.
2. Description of the Related Art
A BMFET, as a kind of short channel junction field effect transistor (JEFT), improves the current capability thereof through a conductivity modulation of a drift region under a forward biasing of the gate junction. The BMFET is very promising switching device for high-frequency and high-voltage applications, owing to the low forward voltage drop and the high switching speed.
FIG. 1 shows a sectional view of a vertical BMFET, separate element. On a N+ substrate 10 of a drain region is formed a N- drift region 11 of epitaxial layer. In a part of the drift region 11 are formed P+ gate regions 12 and in another part of the drift region 11 is formed N+ source region 13 surrounded by P+ gate regions 12. A drain electrode 17, a gate electrode 15 and a source electrode 16 are respectively disposed on the drain region 10, the gate regions 12 and the source region 16. Between the gate electrodes 15 and the source electrode 16 are disposed insulating layers 14.
The important feature of the BMFET cell geometry is the channel width between two gate regions under N+ source region. In the normally-off BMFET, a built-in voltage of the junction between P+ gate region 15 and N- drift region 12 can deplete the channel region with width "c" and also create a potential barrier into the channel sufficiently enough to prevent a large electron emission from the source region to the drain region.
In the normally-on BMFET, the conductivity modulation of the drift region 11 with high resistivity occurs by the hole injection under the forward gate-source bias. Accordingly, very low resistance and higher current gain can be obtained.
As one method for apply the vertical BMFET having such an electrical characteristic to an integrated chip, on an epitaxial substrate the lateral BMFET is formed. However, in that case, the parasitic bipolar junction transistor (BJT) caused by the vertical P/N junction is generated and thus the power consumption is increased. Therefore, it has required that a technique which embodies a lateral BMFET suitable for the integrated chip (IC) of power device, with maintaining the electrical characteristic of the conventional vertical BMFET.
On the other hand, a SOI device, recently used widely in the power IC device, the junction capacitance between the substrate and the source/drain regions is almost not occurred because of an insulation region formed on the substrate and thus fast switching speed is possible. Also, since the leakage current into the substrate is suppressed, the SOI power IC device can used under high temperature. Accordingly, the system using SOI substrate for the power IC device has been studied, and there is, as such power IC device, a MOS gate lateral power device like LIGBT (Lateral Insulated Gate Bipolar Transistor), LMCT (Lateral MOS-Controlled Thyristor) and LDMOS (Lateral DMOS). The LDMOS has higher on-resistance than the bipolar device because of the electrons of the majority carrier, so the large power is consumed. However, the LDMOS has fast switching speed. The LIGBT or LMCT has higher current capability and lower on-resistance but the switching speed is rather low owing to the recombination of hole being a minority carrier. That is, although the vertical BMEFT has good electrical characteristic, in case where the BMFET is manufactured for IC the parasitic BJT current path is generated owing to the P/N junction. And, the MOS gate lateral power device using SOI substrate has large on-resistance or low switching speed.